SPI DMA control register
| DMA_OUTFIFO_EMPTY | Records the status of DMA TX FIFO. 1: DMA TX FIFO is not ready for sending data. 0: DMA TX FIFO is ready for sending data. |
| DMA_INFIFO_FULL | Records the status of DMA RX FIFO. 1: DMA RX FIFO is not ready for receiving data. 0: DMA RX FIFO is ready for receiving data. |
| DMA_SLV_SEG_TRANS_EN | Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable. |
| SLV_RX_SEG_TRANS_CLR_EN | 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done. |
| SLV_TX_SEG_TRANS_CLR_EN | 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done. |
| RX_EOF_EN | 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans. |
| DMA_RX_ENA | Set this bit to enable SPI DMA controlled receive data mode. |
| DMA_TX_ENA | Set this bit to enable SPI DMA controlled send data mode. |
| RX_AFIFO_RST | Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer. |
| BUF_AFIFO_RST | Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer. |
| DMA_AFIFO_RST | Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer. |